The present invention relates to a dynamic memory composed of semiconductor elements, and more particularly to a circuit for precharging the bit lines of the dynamic memory.
Dynamic memories employing one-transistor type memory cells have been predominately utilized as large capacity memories. The one-transistor type memory cell is comprised of a storage capacitor and a transfer gate MOS transistor connected between the storage capacitor and a bit line and having a gate coupled to a word line. In order to achieve high sensitivity detection of a stored signal in a selected memory cell, a differential type sense amplifier is provided for each pair of bit lines. Prior to access operation, each pair of bit lines are precharged to a power voltage. Then, one of a pair of bit lines is subjected to a change in potential due to the content of a selected memory cell while a charge stored in a dummy cell (storing a charge intermediate that corresponding to logic "1" and "0" states of the memory cell) is applied to the other bit line of the bit line pair. Then a sense amplifier is enabled to amplify the difference in potential between the bit lines of the bit line pair such that one of the bit lines is discharged from the power voltage to a ground potential while the other bit line maintains the power voltage. Recently, an improved technique for precharging bit lines was proposed. According to this technique, after the potentials on the pair of bit lines are discriminated into the power voltage V.sub.cc and ground, respectively, the pair of bit lines are short-circuited. Thus, the potential of the pair of bit lines is set to approximately half the power voltage i.e. 1/2 V.sub.cc due to charge division by the pair of bit lines. This technique is advantageous in that the power consumption of the memory can be significantly reduced, and it is possible to eliminate the dummy cell which has been necessary to operate the sense amplifier. However, in the bit line pair, the potential of the higher potential side bit line is only half the power voltage or less when amplification by a differential sense amplifier is completed. Therefore, in order to re-write the power voltage to the selected memory cell storing a "1" for refreshing the "1" value of the selected memory cell and to raise the higher potential side bit line to the power voltage for subsequent short-circuiting as explained above, the higher potential side bit line is raised in potential to the power voltage V.sub.cc by an active pull-up circuit employing a boosting capacitor through which the power voltage is applied to the higher potential side bit line. However, when a pair of bit lines are short-circuited, the boosting capacitor is also connected to the pair of bit lines, particularly to the higher potential side bit line. Also in this instance, certain regions of transistors of the sense amplifier are connected to the short-circuited bit lines to impose a capacitance thereon. Accordingly, the resultant potential remaining on the pair of bit lines does not reach exactly half the power voltage but takes a value less than the latter. As a result, the voltage set at the pair of bit lines shifts from the center value between the "1" and "0" values as stored in respective memory cells. Thus, the differential voltage between the precharged potential of a bit line and a potential stored in a selected memory cell is different according to whether the selected memory cell stores a "1" or "0". This means that the operational margin for a sense amplifier varies according to the content stored in the selected memory cell, resulting in unstable operation.